Overview of the EDA Process
Because chip fabrication is expensive and time consuming, a chip designer often uses computer-aided design (CAD) tools to simulate a particular design before actually fabricating the chip in silicon. The CAD tools used for designing and simulating the functionality's of integrated circuits (ICs) are generally known as EDA systems. Using an EDA system, a circuit designer can simulate a particular design to make sure that it falls within certain constraints, such as die area and power consumption, before the design is actually fabricated. If the simulated results do not fall within a desirable range of values, the circuit designer may modify the design and rerun the simulations until acceptable results are achieved.
In order to simplify the IC design process, EDA systems typically include a library of cells which model various common combinational and sequential logic circuits. Some examples of these common library cells include multiplexed cells and arithmetic logic units (ALUs) cells. These cell libraries provide the components or "building blocks" that an IC designer can use to build a complex chip. In addition to storing the logic behavior of the "building blocks," the cell libraries also contain information regarding the timing delays of the cells, the amount of die area the cells will occupy, the amount of power the cells will consume, etc. Using these information, the EDA system will then be able to calculate various characteristics of an IC composed from these library cells. Naturally, in order to for an EDA system to provide precise calculations, each cell must be accurately characterized. That is, the library developers must accurately estimate the timing delays, the die area, power consumption, etc., of each cell within the library.
Conventionally, the power consumption characteristics, or power behavior, of a cell is exhaustively characterized. In the conventional exhaustive characterization method, each and every possible input transition pattern is applied to the cell, and the power consumed is measured by well known simulation software such as SPICE or PowerMill for each input transition pattern. The conventional method, while accurate, is only applicable to characterizing simple cells with relatively few inputs. For complex cells, or macrocells, this conventional method is impractical. The reason is that the number of simulations required to exhaustively characterize a cell exponentially increases as the number of cell input increases. Particularly, if there are N inputs, the number of simulation required for single input change characterization would be 2.sup.N *N. Thus, when the number of input is large, e.g. more than 32, a very large number of simulations would be required. Even when state of the art computer systems with multiple high-speed microprocessors are used, such characterization processes can take more than weeks. Given the short development cycle of today's IC market, such a long simulation time is unacceptable.
In addition to the long simulation time, the conventional characterization method produces raw data files that are extremely large. Not only do these raw data files require a large amount of memory and storage space, performance of power estimation tools are also significantly hindered.